Semiconductor devices, such as MOSFETs (metal oxide semiconductor field effect transistors), may have asymmetrically doped source and drain regions to increase drive currents and reduce parities. In the prior art, the asymmetrical source and drain doped regions may have different dopants or different numbers of implanted regions. In addition, to form the different dopant regions, spacers on either side of a gate electrode may be different shapes or sizes. While these prior art techniques allow for increased drive current, to form these asymmetrically doped semiconductor devices additional process steps are used that undesirably increase cycle time. Therefore, a need exists for obtaining the advantages of asymmetrically doped source and drain regions without dramatically increasing cycle time.